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Assembler instructions in RCPU



1. Intro
  1. This is a RISC type CPU.
  2. 'Byte' = 8 bits do not exist. Instruction code and operand have the size of memory. If memory is 64bits, Instruction code is 64 bit and operand is 64 bits too. In Double conveyer in direct addressing operand is 2x64 bits, 2 memory addresses.
  3. CPU consist 3 units: Integer unit, Double unit and Address unit.
2. Instruction Format
Instruction format
3. Addressing Methods
  1. Direct addressing.
    Load register with value from the operand.
    1. I: rA <-- #23; Integer conveyer: load register rA with 23
    2. D: rA <-- #23.12; Double conveyer: load register rA with 23.12
    3. A: rX1 <-- #10; Address conveyer: load register rX1 with 10
    # is the sign for direct addressing.
  2. Absolute addressing.
    Load register with value from address in the operand. The operand is absolute address in memory.
    1. I: rA <-- M23; Integer conveyer: load register rA with value from address 23
    2. D: rA <-- M20; Double conveyer: load register rA with value from address 20
    3. A: rX1 <-- M10; Address conveyer: load register rX1 with value from address 10
    M - mean memory. M120 is Memory address 120.
  3. Index addressing.
    Load register with value from address, calculated from index registers / registers in Address unit excluding rMaxX / and the operand.

    M = rB[1,2,3,none] + rX[1,2,3,none] + operand.

    M - memory address.
    rB[1,2,3, none] is one of rB1, rB2, rB3 or nothing.
    rX[1,2,3, none] is one of rX1, rX2, rX3 or nothing.
    Index addressing is not possible for Address unit.

    1. I: rA <-- M[rBs1, rX1] 5; Integer conveyer: load register rA with value from address = rBs1 + rX1 + 5
    2. D: rB <-- M[rBs2,] 10; Double conveyer: load register rB with value from address = rBs2 + 10
    3. I: rB <-- M[rBs1, rX3]0; Integer conveyer: load register rA with value from address = rBs1 + rX3 + 0
4. Instructions by Conveyers
4.1 Integer Conveyer
4.1.1 Memory --> Register       MR
Move data from Memory to integer register. Load integer register from memory. Registers are rA and rB.

1. I: rA <-- #23; Integer conveyer: load register rA with 23
2. I: rA <-- M[rBs1, rX1] 5; Integer conveyer: load register rA with value from address = rBs1 + rX1 + 5
4.1.2 Register --> Memory       RM
Move data from integer register to Memory. Store integer register in memory.
It is just a kind of interpretation. Are they registers (read only) or instructions.
Here is possible only Absolute and Index addressing.


rA-Store rA in Memory.
rB-Store rB in Memory.
AplsB-Store rA + rB in Memory.
AmnsB-rA - rB
BmnsA-rB - rA
AmulB-rA * rB
AdivB-rA / rB
BdivA-rB / rA
sortAB-Sort in AB or BA order. Branches: 1. None. 2. If exchange. 3. If not exchange.
IfAB-Branch If registers rA, rB:   ==, >, =>, <=, <
push-Push register in stack.
pop-Pop register from stack.
AandB-rA & rB
AorB-rA || rB
AxorB-rA ^ rB
AshlB-left shift rA with rB & 63
AshrB-right shift rA with rB & 63
AshrrB-logical right shift rA with rB & 63


1. I: AplsB --> M120Integer conveyer: Calc rA + rB and store in M120
2. I: AmulB --> M[rBs1, rX2] 5Integer conveyer: Calc rA*rB and store in address = rBs1 + rX2 + 5
3. I: AandB --> M[rBs2, rX2] 10Integer conveyer: Calc rA & rB and store in address = rBs2 + rX2 + 10
4. I: if ( A > B ) jump M[rBs3, rX3] Integer conveyer: If A > B jump to address = rBs3 + rX3
5. I: if ( A > B ) jump M[rBs3, ] Integer conveyer: If A > B jump to address = rBs3
6. I: SortAB > & IfExch M[rBs1, rX1]20Integer conveyer: Sort rA, rB (rA should be > rB; exchange if needed). If there is exchange jump to address = rBs1 + rX1 + 20
7. I: push rA Integer conveyer: push rA in stack.
7. I: pop rB Integer conveyer: Pop rB from stack.
4.2 Double Conveyer
4.2.1 Memory --> Register       MR
The instructions are the same as in Integer conveyer. Instead prefix 'I' using 'D'.
4.2.2 Register --> Memory       RM
The instructions are the same as in Integer conveyer. Instead prefix 'I' using 'D'.
Logical and Shift operations do not exist here.
4.3 Address Conveyer
Addressing methods:
Here are possible only direct and absolute addressing methods.
Registers:
1. rIPInstruction pointer
2. rSPStack pointer
3. rBs1Base register 1
4. rBs2Base register 2
5. rBs3Base register 3
6. rX1Index register 1
7. rX2Index register 2
8. rX3Index register 3
9. rMaxXMax X register. Used for loops over memory to indicate max X value.
4.3.1 Memory --> Register       MR
Move data from Memory to address unit register. Load integer register from memory.

1. A: rBs1 <-- #100Load rBs1 with 100.
2. A: rBs2 <-- M120Load rBs2 from address 120.
3. A: rIP <-- #200Load IP with 200. Equal to JUMP 200.
4. A: IncX rX1 #2Increment rX1 with 2.
5. A: IfMaxX rX1 < rMaxX ; M300If rX1 < rMaxX , load address from 300 and JUMP to it.
6. A: push rX1Push rX1 in stack.
4.3.2 Register --> Memory       RM
Store data from register to memory.

1. A: rBs1 --> M100Store rBs1 in address 100.
2. A: rX3 --> M120 Store rX3 in address 120.
5. Register --> Register       RR
Move data from register to register. When move data from double to integer register, take int part only.

Source --> Destination
Conveyer : Register --> Conveyer : Register


1. I: rA --> I: rB Copy int rA in int rB
2. I: AplsB --> I: rACalc rA + rB and store in rA. All are integer.
3. D: rA --> I: rB Copy double rA in integer rB. Integer part only.
4. I: AmnsB --> A: rX1Calc I conveyer rA * rB and store int Address conveyer rX1