My dream CPU
ComputerThis panel contain panels which displays state for all CPU modules.
- Shows cached instructions. Address and instruction.
- Integer registers rA and rB.
- Display states for Integer calculate conveyer/unit.
- Double registers rA and rB
- Display states for Double calculate conveyer/unit.
- Cache for integer results.
- Cache for double results.
- Displays address registers.
Debugger Menu- Generates 1 clock impulse by default, or choice from combo box clock's per click.
- Open new modal window in which is displayed memory. Use it to see result of program execution.
- Open new modal window. Here You can set:
'Frequency ratio IO-BUS/CPU',
'Instruction cache size,
'Integer cache size',
'Double cache size',
'Branch predict' - for instructions with branch start filling alternate Stage1 and Stage 2 from position predicted memory address.
ProgramThis tab display loaded program. Highlighted line is currently executed line.
Execution LogExecution log displays state and last operation in conveyer execution stages.
Clock - clock number.
Stg1 - previous state for stage 1
Stage 1 - Shows last operation for Stage1. Goal of stage 1 is to load instruction and operand.
Stg2 - previous state for stage 3
Stage 2 - Shows last operation for Stage3. Goal of stage 3 is to execute the instruction.
Stg3 - previous state for stage 4
Stage 3 - Shows last operation for Stage4. Goal of stage 4 is to write result in memory, if is needed.
StatisticsStatistics tab displays statistics about conveyer stages. How many times they are in states: Empty, Work, Wait to send.
If 'Branch predict' is enabled, statistics for Stage1 and Stage2 is wrong!
Program InfoProgram info tab displays Common information about the program.